A method that predicts line-level timing and congestion issues directly from Verilog code using CL-Verilog embeddings and gradient-boosted classifiers.
Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond
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abstract
Integrated circuits and electronic systems, as well as design technologies, are evolving at a great rate -- both quantitatively and qualitatively. Major developments include new interconnects and switching devices with atomic-scale uncertainty, the depth and scale of on-chip integration, electronic system-level integration, the increasing significance of software, as well as more effective means of design entry, compilation, algorithmic optimization, numerical simulation, pre- and post-silicon design validation, and chip test. Application targets and key markets are also shifting substantially from desktop CPUs to mobile platforms to an Internet-of-Things infrastructure. In light of these changes in electronic design contexts and given EDA's significant dependence on such context, the EDA community must adapt to these changes and focus on the opportunities for research and commercial success. The CCC workshop series on Extreme-Scale Design Automation, organized with the support of ACM SIGDA, studied challenges faced by the EDA community as well as new and exciting opportunities currently available. This document represents a summary of the findings from these meetings.
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VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
A method that predicts line-level timing and congestion issues directly from Verilog code using CL-Verilog embeddings and gradient-boosted classifiers.