An FPGA accelerator called DTM trains Vanilla and Coalesced Tsetlin Machines on-chip with runtime reconfiguration, reporting higher energy efficiency than prior FPGA training designs.
Convergence of edge computing and deep learning: A comprehensive survey,
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Dynamic Tsetlin Machine Accelerators for On-Chip Training at the Edge using FPGAs
An FPGA accelerator called DTM trains Vanilla and Coalesced Tsetlin Machines on-chip with runtime reconfiguration, reporting higher energy efficiency than prior FPGA training designs.