NEMESIS generates SPICE-verified OTA performance equations from netlist plus schematic via multimodal LLM generation, RAG, and iterative SPICE repair, with <7% average error and ~4622× post-convergence speedup on five topologies.
Simulation-based generation of posynomial performance models for the sizing of analog integrated circuits,
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NEMESIS: NEtlist-Driven Modeling and Equation Synthesis with Inversion-Aware SPICE Anchoring
NEMESIS generates SPICE-verified OTA performance equations from netlist plus schematic via multimodal LLM generation, RAG, and iterative SPICE repair, with <7% average error and ~4622× post-convergence speedup on five topologies.