Controlled FPGA experiments on RISC-V show that adding multiply-divide instructions doubles CoreMark throughput but slightly hurts Dhrystone, pipeline deepening to 8 stages raises frequency and throughput by 71% at the cost of 41% lower efficiency, and 32-bit designs use far fewer resources than 64-
The optimum pipeline depth for a microprocessor
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RV-IM100: Quantifying ISA Extension, Datapath Width, and Pipeline Depth Trade-offs in RISC-V Microarchitectures
Controlled FPGA experiments on RISC-V show that adding multiply-divide instructions doubles CoreMark throughput but slightly hurts Dhrystone, pipeline deepening to 8 stages raises frequency and throughput by 71% at the cost of 41% lower efficiency, and 32-bit designs use far fewer resources than 64-