Pauli Envelope framework enables optimal loss-distance correction (d_loss ~ d) for rotated surface codes via Mid-SWAP circuits and Envelope-MLE decoder, with simulations showing up to 40% higher thresholds.
Fast correlated decoding of transversal logical algorithms
9 Pith papers cite this work. Polarity classification is still indexing.
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Union-find decoder for surface code achieves finite threshold under circuit-level stochastic errors with quasi-polylog parallel runtime bound.
Knill error correction reduces circuit-level decoding for quantum LDPC codes to the simpler code-capacity decoder while remaining fault-tolerant under locally decaying noise.
A qubit-reduction method for hypergraph product codes preserves dimension, distance, and fault-tolerance properties, producing smaller codes such as [[441,64,6]] from [[610,64,6]] with comparable noise performance and compatibility with logical gates.
The biplanar architecture maps Fermi-Hubbard spin sectors to two planes, eliminating swaps and cutting each Trotter step depth to 4t_synth + 90 logical timesteps versus 6t_synth + 354 in single-plane methods, yielding an estimated 2-hour runtime for L=8 with 1.35 million physical qubits under a 1% 1
Generalizes stat-mech mapping from toric code memories to transversal Clifford circuits, mapping tCNOT to random Ashkin-Teller and 4-body Ising models and estimating reduced thresholds of p=0.080 and p>=0.028.
Comparative analysis of fault-tolerant interfaces for modular quantum computing using surface codes, including novel grow-and-distil protocols, to determine optimal strategies across hardware parameters for low logical error rates.
Proposes QLOPS as an integrated benchmarking metric for FTQC hardware that factors in code rates, decoder throughput, latency, and accuracy, illustrated via RSA-2048 factoring resource estimates.
citing papers explorer
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Achieving Optimal-Distance Atom-Loss Correction via Pauli Envelope
Pauli Envelope framework enables optimal loss-distance correction (d_loss ~ d) for rotated surface codes via Mid-SWAP circuits and Envelope-MLE decoder, with simulations showing up to 40% higher thresholds.
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Proof of a finite threshold for the union-find decoder
Union-find decoder for surface code achieves finite threshold under circuit-level stochastic errors with quasi-polylog parallel runtime bound.
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Simplified circuit-level decoding using Knill error correction
Knill error correction reduces circuit-level decoding for quantum LDPC codes to the simpler code-capacity decoder while remaining fault-tolerant under locally decaying noise.
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Spatial overhead reduction for 2D hypergraph product codes
A qubit-reduction method for hypergraph product codes preserves dimension, distance, and fault-tolerance properties, producing smaller codes such as [[441,64,6]] from [[610,64,6]] with comparable noise performance and compatibility with logical gates.
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Two Layers, No Swaps: Biplanar SPOQC Architecture Improves Runtime of Fermi-Hubbard Simulation
The biplanar architecture maps Fermi-Hubbard spin sectors to two planes, eliminating swaps and cutting each Trotter step depth to 4t_synth + 90 logical timesteps versus 6t_synth + 354 in single-plane methods, yielding an estimated 2-hour runtime for L=8 with 1.35 million physical qubits under a 1% 1
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Rigorous estimation of error thresholds of transversal Clifford logical circuits
Generalizes stat-mech mapping from toric code memories to transversal Clifford circuits, mapping tCNOT to random Ashkin-Teller and 4-body Ising models and estimating reduced thresholds of p=0.080 and p>=0.028.
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Fault-tolerant interfaces for modular quantum computing on diverse qubit platforms
Comparative analysis of fault-tolerant interfaces for modular quantum computing using surface codes, including novel grow-and-distil protocols, to determine optimal strategies across hardware parameters for low logical error rates.
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Benchmarking fault-tolerant quantum computing hardware via QLOPS
Proposes QLOPS as an integrated benchmarking metric for FTQC hardware that factors in code rates, decoder throughput, latency, and accuracy, illustrated via RSA-2048 factoring resource estimates.
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