A RISC-V core with a runtime-reconfigurable multiplier achieves 44-68% power reduction in exact and approximate modes while preserving 1.89 DMIPS/MHz performance for error-tolerant neural network tasks.
RISC-V instruction set architecture exten- sions: A survey
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A Reconfigurable Multiplier Architecture for Error-Resilient Applications in RISC-V Core
A RISC-V core with a runtime-reconfigurable multiplier achieves 44-68% power reduction in exact and approximate modes while preserving 1.89 DMIPS/MHz performance for error-tolerant neural network tasks.