RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
The EPFL Logic Synthesis Libraries
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abstract
We present a collection of modular open source C++ libraries for the development of logic synthesis applications. These libraries can be used to develop applications for the design of classical and emerging technologies, as well as for the implementation of quantum compilers. All libraries are well documented and well tested. Furthermore, being header-only, the libraries can be readily used as core components in complex logic synthesis systems.
fields
cs.AR 2years
2026 2representative citing papers
Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.
citing papers explorer
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RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits
RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
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Miter-Aware LUT Mapping: Aligning Structure and Solvability for Efficient Logic Equivalence Checking
Joint LUT mapping of golden and implementation circuits, combined with Gaussian-guided XOR modeling and solver-oriented LUT selection, reduces SAT-based logic equivalence checking runtime by up to 92.1%.