An FPGA transceiver serializes time-encoded bit patterns at 10 Gbps to produce a calibration-free 100 ps-resolution digital-to-time converter.
Title resolution pending
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
eess.SP 1years
2024 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
A reconfigurable calibration-free digital-to-time converter based on a high-speed transceiver
An FPGA transceiver serializes time-encoded bit patterns at 10 Gbps to produce a calibration-free 100 ps-resolution digital-to-time converter.