A method that predicts line-level timing and congestion issues directly from Verilog code using CL-Verilog embeddings and gradient-boosted classifiers.
Using graph neural networks for timing esti- mations of rtl intermediate representations,
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VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
A method that predicts line-level timing and congestion issues directly from Verilog code using CL-Verilog embeddings and gradient-boosted classifiers.