A simulated annealing refinement of tensor network partitionings for distributed contraction lowers estimated computational and memory cost by about 8x on average versus naive partitioning on MQT Bench circuits.
Massively Parallel Tensor Network State Algorithms on Hybrid CPU-GPU Based Architectures
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abstract
The interplay of quantum and classical simulation and the delicate divide between them is in the focus of massively parallelized tensor network state (TNS) algorithms designed for high performance computing (HPC). In this contribution, we present novel algorithmic solutions together with implementation details to extend current limits of TNS algorithms on HPC infrastructure building on state-of-the-art hardware and software technologies. Benchmark results obtained via large-scale density matrix renormalization group (DMRG) simulations are presented for selected strongly correlated molecular systems addressing problems on Hilbert space dimensions up to $2.88\times10^{36}$.
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Optimizing Tensor Network Partitioning using Simulated Annealing
A simulated annealing refinement of tensor network partitionings for distributed contraction lowers estimated computational and memory cost by about 8x on average versus naive partitioning on MQT Bench circuits.