RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
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MailoHLS combines LLM semantic reasoning and GNN structural modeling with multi-adapter PEFT and Pareto optimization to produce near-Pareto-optimal HLS pragma configurations, reporting up to 12.42x latency speedup on seen kernels and 10.2x on unseen ones.
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RTLScout: Joint Agentic Code and Synthesis Optimization for Efficient Digital Circuits
RTLScout combines LLM-driven agentic RTL code optimization with synthesis and architecture sweeps to achieve 35% area and 45% delay reductions on a 16-bit IEEE-754 floating-point multiplier compared to baseline designs in ASAP7 technology.
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MailoHLS: Multi-Adapter Structure-Aware Learning for Pareto-Driven HLS Pragma Optimization
MailoHLS combines LLM semantic reasoning and GNN structural modeling with multi-adapter PEFT and Pareto optimization to produce near-Pareto-optimal HLS pragma configurations, reporting up to 12.42x latency speedup on seen kernels and 10.2x on unseen ones.