LUNA achieves up to 10.95x area reduction and 30% lower latency for qubit readout using integrator-based preprocessing and LogicNet LUT synthesis with minimal fidelity loss.
Retrieved November 01, 2025 from https://github.com/Xilinx/ logicnets/tree/master
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LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
LUNA achieves up to 10.95x area reduction and 30% lower latency for qubit readout using integrator-based preprocessing and LogicNet LUT synthesis with minimal fidelity loss.