A CCD-level, workload-aware thread orchestration framework for in-memory vector ANNS delivers up to 3.7x higher throughput and 30-90% lower P50/P999 latency on multi-core CPUs by improving cache use and load balance.
https://www.amd.com/content/dam/amd/en/documents/epyc-technical- docs/white-papers/58015-epyc-9004-tg-architecture-overview.pdf
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CCD-Level and Load-Aware Thread Orchestration for In-Memory Vector ANNS on Multi-Core CPUs
A CCD-level, workload-aware thread orchestration framework for in-memory vector ANNS delivers up to 3.7x higher throughput and 30-90% lower P50/P999 latency on multi-core CPUs by improving cache use and load balance.