Reelay translates LTL, MTL, and STL specifications into synchronous dataflow computation graphs for efficient online runtime verification supporting discrete and dense time semantics.
Monitoring prop- erties of analog and mixed-signal circuits
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.LO 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Reelay: Online Temporal Logic Monitoring Framework
Reelay translates LTL, MTL, and STL specifications into synchronous dataflow computation graphs for efficient online runtime verification supporting discrete and dense time semantics.