A chiplet-based RISC-V SoC with modular AI accelerators and cross-chiplet optimizations reports 14.7% latency reduction and 40.1% efficiency gain versus basic chiplet designs on standard edge AI benchmarks.
The use and evaluation of yield models in integrated circuit manufacturing,
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Chiplet-Based RISC-V SoC with Modular AI Acceleration
A chiplet-based RISC-V SoC with modular AI accelerators and cross-chiplet optimizations reports 14.7% latency reduction and 40.1% efficiency gain versus basic chiplet designs on standard edge AI benchmarks.