Presents scalable packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE for VLA ML code generation on Arm SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks.
In 10 Proceedings of the 29th ACM international conference on architectural support for programming languages and operating systems, volume 2(2024), pp
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Scalable Packed Layouts for Vector-Length-Agnostic ML Code Generation
Presents scalable packed layouts and extensions to tiling/fusion/vectorization in MLIR/IREE for VLA ML code generation on Arm SVE, achieving up to 1.45x speedup over NEON and outperforming PyTorch frameworks.