Proposes a feasibility taxonomy of 20 hardware-level AI compute governance mechanisms organized by monitoring, verification, and enforcement, with mappings to regulatory scenarios that highlight immaturity of treaty-verification tools.
Toward a global regime for compute governance: Building the pause button
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This paper proposes a taxonomy of LLM harms in five categories and suggests mitigation strategies plus a dynamic auditing system for responsible development.
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Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification
Proposes a feasibility taxonomy of 20 hardware-level AI compute governance mechanisms organized by monitoring, verification, and enforcement, with mappings to regulatory scenarios that highlight immaturity of treaty-verification tools.
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LLM Harms: A Taxonomy and Discussion
This paper proposes a taxonomy of LLM harms in five categories and suggests mitigation strategies plus a dynamic auditing system for responsible development.