A joint SAR despeckling and compression model was deployed on an FPGA, where hardware-friendly changes like ReLU instead of GDN improved performance, residual blocks were not worth their 10x compute cost, and the FPGA proved most energy-efficient.
Joint compression and despeckling by SAR representation learning,
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Hardware-Aware Deployment of Joint SAR Compression and Despeckling on FPGA
A joint SAR despeckling and compression model was deployed on an FPGA, where hardware-friendly changes like ReLU instead of GDN improved performance, residual blocks were not worth their 10x compute cost, and the FPGA proved most energy-efficient.