TicToc integrates TIC and TOC DRAM cache organizations with dirty-bit optimizations to deliver 10% speedup over baseline TIC in 4GB DRAM cache evaluations against 3D-XPoint memory while using only 34KB SRAM.
Fundamental latency trade-off in architecting dram caches: Outperforming impractical sram-tags with a simple and practical design,
2 Pith papers cite this work. Polarity classification is still indexing.
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Pith papers citing it
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cs.AR 2years
2019 2verdicts
UNVERDICTED 2representative citing papers
RRIP-AOB and ETR enable stateful replacement in 2GB DRAM caches for 18% speedup using <1KB SRAM by reducing state-tracking bandwidth 70%.
citing papers explorer
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TicToc: Enabling Bandwidth-Efficient DRAM Caching for both Hits and Misses in Hybrid Memory Systems
TicToc integrates TIC and TOC DRAM cache organizations with dirty-bit optimizations to deliver 10% speedup over baseline TIC in 4GB DRAM cache evaluations against 3D-XPoint memory while using only 34KB SRAM.
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To Update or Not To Update?: Bandwidth-Efficient Intelligent Replacement Policies for DRAM Caches
RRIP-AOB and ETR enable stateful replacement in 2GB DRAM caches for 18% speedup using <1KB SRAM by reducing state-tracking bandwidth 70%.