Derives scaling laws showing analog front-end power scales at least as SNDR to the 3/2 and can be reduced at least 20x by adapting to fading while meeting minimum performance.
A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS,
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Low Power Receiver Front Ends: Scaling Laws and Applications
Derives scaling laws showing analog front-end power scales at least as SNDR to the 3/2 and can be reduced at least 20x by adapting to fading while meeting minimum performance.