A new Verilog vectorizer on CIRCT yields 28% faster elaboration and 51% lower memory use for the Jasper formal verification tool across 1,157 ChiBench designs.
Chibench: a bench- mark suite for testing electronic design automation tools, 2024.https: //arxiv.org/abs/2406.06550
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.PL 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Vectorization of Verilog Designs and its Effects on Verification and Synthesis
A new Verilog vectorizer on CIRCT yields 28% faster elaboration and 51% lower memory use for the Jasper formal verification tool across 1,157 ChiBench designs.