Monolithic 3D integration of NCL asynchronous circuits achieves 44% area reduction, 31% delay reduction, and 17% power reduction in an unsigned array multiplier under conservative wirelength assumptions.
Compact 6T- SRAM using bottom-gate transistor in FD -SOI process for Monolithic- 3D Integra - tion
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Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits
Monolithic 3D integration of NCL asynchronous circuits achieves 44% area reduction, 31% delay reduction, and 17% power reduction in an unsigned array multiplier under conservative wirelength assumptions.