An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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quant-ph 2years
2026 2verdicts
UNVERDICTED 2representative citing papers
A family of quantum LDPC codes with encoding rates exceeding 1/2 achieves logical error rates of 10^{-13} per round on atom arrays under 0.1% circuit noise using hierarchical decoding.
citing papers explorer
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Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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Towards Ultra-High-Rate Quantum Error Correction with Reconfigurable Atom Arrays
A family of quantum LDPC codes with encoding rates exceeding 1/2 achieves logical error rates of 10^{-13} per round on atom arrays under 0.1% circuit noise using hierarchical decoding.