A nine-transistor current-mode bistable memory cell in 180 nm CMOS is presented with independent tuning of threshold, hysteresis, and gain, shown via schematic simulations for spike-based logic gates and recurrent neural units.
Memory devices and applications for in-memory computing
3 Pith papers cite this work. Polarity classification is still indexing.
3
Pith papers citing it
citation-role summary
background 2
citation-polarity summary
years
2026 3roles
background 2polarities
background 2representative citing papers
An MTJ-based logic-in-memory design performs fully parallel stochastic bit-stream generation and arithmetic without external random number generators by exploiting device stochasticity.
citing papers explorer
-
A Fully Tunable Ultra-Low Power Current-Mode Memory Cell in Standard CMOS Technology
A nine-transistor current-mode bistable memory cell in 180 nm CMOS is presented with independent tuning of threshold, hysteresis, and gain, shown via schematic simulations for spike-based logic gates and recurrent neural units.
-
Maximizing Memory-Level Parallelism via Integrated Stochastic Logic-in-Memory Architectures
An MTJ-based logic-in-memory design performs fully parallel stochastic bit-stream generation and arithmetic without external random number generators by exploiting device stochasticity.
- Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations