RTL-Breaker shows that fine-tuning an LLM on a small fraction of poisoned Verilog samples can make it generate malicious RTL code when a specific trigger appears, while still passing VerilogEval functional checks.
Llms and the future of chip design: Unveiling secu- rity risks and building trust,
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RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
RTL-Breaker shows that fine-tuning an LLM on a small fraction of poisoned Verilog samples can make it generate malicious RTL code when a specific trigger appears, while still passing VerilogEval functional checks.