Integration of OPS intermediate representation as a GPU backend in Devito DSL yields speedups over the core backend for structured-mesh finite-difference applications.
Multi-level spatial and temporal tiling for efficient hpc stencil computation on many-core processors with large shared caches
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Investigating the OPS intermediate representation to target GPUs in the Devito DSL
Integration of OPS intermediate representation as a GPU backend in Devito DSL yields speedups over the core backend for structured-mesh finite-difference applications.