FASE enables early-stage processor performance validation on FPGA by emulating Linux syscalls via a minimal CPU interface, Host-Target Protocol, and host-side runtime, achieving over 96% accuracy versus full SoC for most workloads.
Symbolic quick error detection using symbolic initial state for pre-silicon verification
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FASE: FPGA-Assisted Syscall Emulation for Rapid End-to-End Processor Performance Validation
FASE enables early-stage processor performance validation on FPGA by emulating Linux syscalls via a minimal CPU interface, Host-Target Protocol, and host-side runtime, achieving over 96% accuracy versus full SoC for most workloads.