A load-aware, spatially-informed voltage regulator activation strategy for DVPD in HPC reduces switching losses 2-3x and holds ~87% efficiency from 5-30% load in simulations while keeping ripple within limits.
Itap: Idle-time-aware power management for gpu execution units,
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Dynamic Power Management Methodology for Distributed Vertical Power Delivery in High-Performance Computing Systems
A load-aware, spatially-informed voltage regulator activation strategy for DVPD in HPC reduces switching losses 2-3x and holds ~87% efficiency from 5-30% load in simulations while keeping ripple within limits.