PoSyn selects standard-cell mappings during synthesis to lower power side-channel leakage, reporting DPA/CPA success rates as low as 3% and 6%, but its theoretical mutual-information guarantee is unsupported.
Aes-based security coprocessor ic in 0.18-muhboxm cmos with resistance to differential power analysis side-channel attacks,
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PoSyn: Secure Power Side-Channel Aware Synthesis
PoSyn selects standard-cell mappings during synthesis to lower power side-channel leakage, reporting DPA/CPA success rates as low as 3% and 6%, but its theoretical mutual-information guarantee is unsupported.