A knowledge graph integrates specs, RTL, and verification feedback to power multi-agent generation of SystemVerilog assertions, yielding 78.5-99.4% formal coverage on seven benchmarks with reduced syntax issues.
Enhanced VLSI Assertion Generation: Conforming to High-Level Specifications and Reducing LLM Hallucinations with RAG,
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Knowledge Graphs, the Missing Link in Agentic AI-based Formal Verification
A knowledge graph integrates specs, RTL, and verification feedback to power multi-agent generation of SystemVerilog assertions, yielding 78.5-99.4% formal coverage on seven benchmarks with reduced syntax issues.