A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.
Neural cache: Bit-serial in-cache acceleration of deep neural networks,
3 Pith papers cite this work. Polarity classification is still indexing.
3
Pith papers citing it
fields
cs.AR 3years
2026 3verdicts
UNVERDICTED 3representative citing papers
AQPIM performs in-memory product quantization of activations for LLMs on PIM hardware, reducing GPU-CPU communication by 90-98.5% and delivering 3.4x speedup over prior PIM methods.
SPARK is a sparsity-aware near-cache ILP accelerator that reuses L1 cache structures to deliver up to 15x speedup and 152x energy reduction versus CPUs on sparse MIPLIB workloads with 1.4% area overhead.
citing papers explorer
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GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.
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AQPIM: Breaking the PIM Capacity Wall for LLMs with In-Memory Activation Quantization
AQPIM performs in-memory product quantization of activations for LLMs on PIM hardware, reducing GPU-CPU communication by 90-98.5% and delivering 3.4x speedup over prior PIM methods.
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A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
SPARK is a sparsity-aware near-cache ILP accelerator that reuses L1 cache structures to deliver up to 15x speedup and 152x energy reduction versus CPUs on sparse MIPLIB workloads with 1.4% area overhead.