A global-local optimization framework automates asynchronous SAR ADC sizing and reports pre-layout simulation results up to 72.2 dB SNDR and 177.3 dB FoM in 65 nm CMOS.
Title resolution pending
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
math.OC 1years
2025 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
A Global-Local Optimization Approach for Asynchronous SAR ADC Design
A global-local optimization framework automates asynchronous SAR ADC sizing and reports pre-layout simulation results up to 72.2 dB SNDR and 177.3 dB FoM in 65 nm CMOS.