Splitting a chip into two stacked 3D tiers and obfuscating the vertical connections protects against both IP theft and targeted hardware-Trojan insertion with moderate PPA overhead.
Protect Your Chip Design Intellectual Property: An Overview
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abstract
The increasing cost of integrated circuit (IC) fabrication has driven most companies to "go fabless" over time. The corresponding outsourcing trend gave rise to various attack vectors, e.g., illegal overproduction of ICs, piracy of the design intellectual property (IP), or insertion of hardware Trojans (HTs). These attacks are possibly conducted by untrusted entities residing all over the supply chain, ranging from untrusted foundries, test facilities, even to end-users. To overcome this multitude of threats, various techniques have been proposed over the past decade. In this paper, we review the landscape of IP protection techniques, which can be classified into logic locking, layout camouflaging, and split manufacturing. We discuss the history of these techniques, followed by state-of-the-art advancements, relevant limitations, and scope for future work.
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2019 1verdicts
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A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects
Splitting a chip into two stacked 3D tiers and obfuscating the vertical connections protects against both IP theft and targeted hardware-Trojan insertion with moderate PPA overhead.