The Min-Sum LDPC decoder is restated as masked matrix reductions and implemented with CUDA kernels that take the parity matrix as a runtime argument, with throughput measured on a CCSDS quasi-cyclic code.
5g nr ldpc decoding performance comparison be- tween gpu & fpga platforms
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A mapping of the Min-Sum decoder to reduction operations, and its implementation using CUDA kernels
The Min-Sum LDPC decoder is restated as masked matrix reductions and implemented with CUDA kernels that take the parity matrix as a runtime argument, with throughput measured on a CCSDS quasi-cyclic code.