An LLM-with-RAG framework that iteratively generates and refines HLS code with pragmas, reporting up to 4x speedups and timing closure across 10 FPGA families.
Conget al., ”FPGA HLS today: successes, challenges, and opportu- nities”
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TimelyHLS: LLM-Based Timing-Aware and Architecture-Specific FPGA HLS Optimization
An LLM-with-RAG framework that iteratively generates and refines HLS code with pragmas, reporting up to 4x speedups and timing closure across 10 FPGA families.