Adding a cache hierarchy, CGRA-specific runahead prefetching, and per-PE cache reconfiguration allows CGRAs to process irregular memory-access kernels at near-ideal speed with 1.27% of the storage.
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Re-thinking Memory-Bound Limitations in CGRAs
Adding a cache hierarchy, CGRA-specific runahead prefetching, and per-PE cache reconfiguration allows CGRAs to process irregular memory-access kernels at near-ideal speed with 1.27% of the storage.