The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.
A Variable and Extended Precision (VRP) Accelerator and its 22 nm soc Implementation
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EPAC: The Last Dance
The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.