An LLM-based system combining specification analysis, waveform analysis, and Monte Carlo Tree Self-Refine generates SystemVerilog assertions that outperform AssertLLM and ChIRAAG on I2C and RV-Timer designs.
Automatically improving llm-based verilog generation using eda tool feedback,
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SANGAM: SystemVerilog Assertion Generation via Monte Carlo Tree Self-Refine
An LLM-based system combining specification analysis, waveform analysis, and Monte Carlo Tree Self-Refine generates SystemVerilog assertions that outperform AssertLLM and ChIRAAG on I2C and RV-Timer designs.