SV-LLM automates SoC security verification with six cooperating LLM agents, reaching 84.8% vulnerability detection accuracy and 82% to 89% bug validation rates on benchmarks the paper does not disclose.
Toward Automated Potential Primary Asset Identification in Verilog Designs
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abstract
With greater design complexity, the challenge to anticipate and mitigate security issues provides more responsibility for the designer. As hardware provides the foundation of a secure system, we need tools and techniques that support engineers to improve trust and help them address security concerns. Knowing the security assets in a design is fundamental to downstream security analyses, such as threat modeling, weakness identification, and verification. This paper proposes an automated approach for the initial identification of potential security assets in a Verilog design. Taking inspiration from manual asset identification methodologies, we analyze open-source hardware designs in three IP families and identify patterns and commonalities likely to indicate structural assets. Through iterative refinement, we provide a potential set of primary security assets and thus help to reduce the manual search space.
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SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models
SV-LLM automates SoC security verification with six cooperating LLM agents, reaching 84.8% vulnerability detection accuracy and 82% to 89% bug validation rates on benchmarks the paper does not disclose.