A wafer-scale design-space exploration method constructs physically feasible design spaces and prunes candidates by a sampled evaluator-disagreement bound, recovering the exhaustive reference optimum in all 70 tested pairs with 4.13x average speedup.
Eval- uating the impacts of reticle requirements in semiconductor wafer fab- rication,
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Fovea: Physical-Implication-Aware Wafer-Scale DSE with Decision-Domain-Guided Cross-Fidelity Refinement
A wafer-scale design-space exploration method constructs physically feasible design spaces and prunes candidates by a sampled evaluator-disagreement bound, recovering the exhaustive reference optimum in all 70 tested pairs with 4.13x average speedup.