Proposes a feasibility taxonomy of 20 hardware-level AI compute governance mechanisms organized by monitoring, verification, and enforcement, with mappings to regulatory scenarios that highlight immaturity of treaty-verification tools.
Principled symbolic validation of enclaves on low-end microcontrollers
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.CR 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Hardware-Level Governance of AI Compute: A Feasibility Taxonomy for Regulatory Compliance and Treaty Verification
Proposes a feasibility taxonomy of 20 hardware-level AI compute governance mechanisms organized by monitoring, verification, and enforcement, with mappings to regulatory scenarios that highlight immaturity of treaty-verification tools.