Algorithms for contention-resilient read/write and CAS registers with O(log P) latency w.h.p. under stochastic scheduler, using O(1) hardware registers, plus a space-latency lower bound.
Bender, Mart \'i n Farach-Colton , Simai He, Bradley C
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Fast Concurrent Primitives Despite Contention
Algorithms for contention-resilient read/write and CAS registers with O(log P) latency w.h.p. under stochastic scheduler, using O(1) hardware registers, plus a space-latency lower bound.