This paper presents a full-system simulation framework that runs a hypervisor and VMs on gem5 with configurable DRAM address mappings, and demonstrates evaluation of two software-based inter-VM RowHammer mitigations.
Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors,
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A Simulation-based Evaluation Framework for Inter-VM RowHammer Mitigation Techniques
This paper presents a full-system simulation framework that runs a hypervisor and VMs on gem5 with configurable DRAM address mappings, and demonstrates evaluation of two software-based inter-VM RowHammer mitigations.