A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.
Compute-in-memory chips for deep learning: Recent trends and prospects
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E-ReCON presents a precision-configurable sparse nvCIM macro with 3T1R ReRAM bitcells and interleaved 10T/28T adder tree achieving up to 419 TOPS/W for both conventional and spiking neural edge inference.
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GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.
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E-ReCON: An Energy- and Resource-Efficient Precision-Configurable Sparse nvCIM Macro for Conventional and Spiking Neural Edge Inference
E-ReCON presents a precision-configurable sparse nvCIM macro with 3T1R ReRAM bitcells and interleaved 10T/28T adder tree achieving up to 419 TOPS/W for both conventional and spiking neural edge inference.