17 nm SiO2 oxide thickness minimizes threshold voltage variability below 63 mV standard deviation in dense 7x7 silicon quantum dot arrays fabricated via 300 mm CMOS and EUV lithography.
Van Damme et al., Advanced CMOS manufacturing of superconducting qubits on 300 mm wafers, Nature 634, 74 (2024)
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Understanding oxide-thickness-dependent variability in dense Si-MOS quantum dot arrays
17 nm SiO2 oxide thickness minimizes threshold voltage variability below 63 mV standard deviation in dense 7x7 silicon quantum dot arrays fabricated via 300 mm CMOS and EUV lithography.