An FPGA accelerator for SkipGPT-style pruned LLMs that fuses router/normalization/attention computation to hide nonlinear latency, packs two FP16 products in each DSP, and serves reused KV entries from on-chip URAM to reach 88-89% bandwidth efficiency.
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SkipOPU: An FPGA-based Overlay Processor for Large Language Models with Dynamically Allocated Computation
An FPGA accelerator for SkipGPT-style pruned LLMs that fuses router/normalization/attention computation to hide nonlinear latency, packs two FP16 products in each DSP, and serves reused KV entries from on-chip URAM to reach 88-89% bandwidth efficiency.