Segmented temperature control reduces Ge diffusion to 5.6-7% of its 650°C value in Si/SiGe superlattices, enabling a 4+4 channel stack with sharp interfaces, preserved pseudomorphic strain, and low roughness.
Demonstration of 3D sequential FD -SOI on CMOS FinFET stacking featuring low temperature Si layer transfer and top tier device fabrication with tier interconnections,
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Si/SiGe multi-channel superlattice structure epitaxial growth with segmented temperature control for Next-Generation Logic Devices
Segmented temperature control reduces Ge diffusion to 5.6-7% of its 650°C value in Si/SiGe superlattices, enabling a 4+4 channel stack with sharp interfaces, preserved pseudomorphic strain, and low roughness.