Monolithic 3D integration of NCL asynchronous circuits achieves 44% area reduction, 31% delay reduction, and 17% power reduction in an unsigned array multiplier under conservative wirelength assumptions.
An analysis of the effect of wire resistance on circuit level performance at the 45-nm technology node
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Monolithic 3D Integration for Null Convention Logic (NCL)-Based Asynchronous Circuits
Monolithic 3D integration of NCL asynchronous circuits achieves 44% area reduction, 31% delay reduction, and 17% power reduction in an unsigned array multiplier under conservative wirelength assumptions.