Single 32-bit sub-channel DDR5 DIMMs transfer full 64-byte cache lines with 40-60% bandwidth degradation in heavy workloads and <10% in latency-bound ones, show AMD incompatibility, and already have native SPD support.
Intel Chief Overclocking Architect Dan Ragland is quoted in the press release endorsing the result, Nov
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Single 32-bit Sub-Channel DDR5 DIMMs: Architecture, Performance Bounds, and Standardisation
Single 32-bit sub-channel DDR5 DIMMs transfer full 64-byte cache lines with 40-60% bandwidth degradation in heavy workloads and <10% in latency-bound ones, show AMD incompatibility, and already have native SPD support.