FPGA lock agents with on-chip tables achieve up to 51X higher TPC-C throughput than CPU baselines by removing DRAM access overhead for lock operations.
Title resolution pending
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
years
2026 2representative citing papers
A vision for a cloud SmartNIC that hides Parquet decoding costs by offloading parsing and filters directly on the network datapath, backed by DuckDB performance estimates.
citing papers explorer
-
FPGA-Accelerated Lock Management and Transaction Processing: Architecture, Optimization, and Design Space Exploration
FPGA lock agents with on-chip tables achieve up to 51X higher TPC-C throughput than CPU baselines by removing DRAM access overhead for lock operations.
-
Should I Hide My Duck in the Lake?
A vision for a cloud SmartNIC that hides Parquet decoding costs by offloading parsing and filters directly on the network datapath, backed by DuckDB performance estimates.